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Board Components
Table 2–9. Ethernet MAC/PHY Pin Table (Continued)
FPGA Pin
A9
C10
D10
B10
A10
E12
D12
J13
J14
F12
G12
J10
J11
C11
B11
C12
B12
D6
G11
70
69
68
66
65
64
63
61
60
59
58
56
55
54
53
51
50
49
48
U4 Pin
Pin Function
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Board Net Name (1)
fe_d13
fe_d14
fe_d15
fe_d16
fe_d17
fe_d18
fe_d19
fe_d20
fe_d21
fe_d22
fe_d23
fe_d24
fe_d25
fe_d26
fe_d27
fe_d28
fe_d29
fe_d30
fe_d31
Note to Table 2–9 :
(1)
Nets fe_a0 and fe_a16 to fe_a23 do not connect to U4.
f
Serial Connector
(J19)
Altera Corporation
May 2007
See www.smsc.com for detailed information about the LAN91C111
device.
J19 is a standard DB-9 serial connector, and is typically used for
communication between the FPGA and a host computer via an RS-232
serial cable. Level-shifting buffer (U52) is used between J19 and the
FPGA, because the FPGA device cannot interface to RS-232 voltage levels
directly.
J19 is able to transmit all RS-232 signals. Alternately, the FPGA design can
use only the signals it needs, such as J19’s RXD and TXD pins. LEDs are
connected to the RXD and TXD signals and visually indicate when data
is being transmitted or received. Figure 6 and Table 2–10 show the pin
connections between the serial connectors and the FPGA.
Reference Manual 2–15
Nios Development Board Cyclone II Edition
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